STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONSstandard by JEDEC Solid

APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGYstandard by JEDEC Solid State Technology Association, 07/01/2008

Addendum No. 1 to 3D Stacked SDRAMAmendment by JEDEC Solid State Technology Association, 12/01/2013

Addendum No. 2 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600Amendment by JEDEC Solid State Technology Association, 10/01/2011

Universal Flash Storage (UFS) Host Controller Interfacestandard by JEDEC Solid State Technology Association, 08/01/2011

POD135 - 1.35 V PSEUDO OPEN DRAIN I/Ostandard by JEDEC Solid State Technology Association, 09/01/2013

Inspection Criteria for Microelectronic Packages and Coversstandard by JEDEC Solid State Technology Association, 05/01/2011

THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD)standard by JEDEC Solid State Technology Association, 07/01/1986

STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 08/01/2001

RF Biased Life (RFBL) Test Methodstandard by JEDEC Solid State Technology Association, 01/01/2013

DDR4 SDRAM Standardstandard by JEDEC Solid State Technology Association, 06/01/2017

TEST METHODS FOR THE COLLECTOR-BASE TIME CONSTANT AND FOR THE RESISTIVE PART OF THE COMMON-EMITTER INPUT IMPEDANCEstandard by JEDEC Solid State Technology