ZENER AND VOLTAGE REGULATOR DIODE RATING VERIFICATION AND CHARACTERIZATION TESTINGstandard by JEDEC Solid State Technology Association, 12/01/2009

DDR4 DATA BUFFER DEFINITION (DDR4DB01)standard by JEDEC Solid State Technology Association,

GDDR5 SGRAMstandard by JEDEC Solid State Technology Association, 09/01/2009

Low Power Double Data Rate 3 SDRAM (LPDDR3)standard by JEDEC Solid State Technology Association, 05/01/2012

FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORINGstandard by JEDEC Solid State Technology Association, 04/01/2017

DESCRIPTION OF 1.8 V CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 04/01/2000

2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTSstandard by JEDEC Solid State Technology Association, 06/01/1999

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESSstandard by JEDEC Solid State Technology Association, 09/01/2004

LOW POWER DOUBLE DATA RATE 2 (LPDDR2)standard by JEDEC Solid State Technology Association, 12/01/2010

ADDENDUM No. 5 to JESD8 - 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY

ADDENDUM No. 3 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-DRAIN VOLTAGE METHOD)Amendment by JEDEC Solid State Technology

PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 03/01/2006