STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTSstandard by JEDEC Solid State Technology

PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATUREstandard by JEDEC Solid State Technology Association, 10/01/2009

INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINESstandard by JEDEC Solid State Technology Association, 11/01/2006

DDR4 REGISTER CLOCK DRIVER (DDR4RCD01)standard by JEDEC Solid State Technology Association, 08/01/2016

DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONSstandard by

HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODTstandard by JEDEC Solid State Technology Association, 10/01/2012

Universal Flash Storage Host Controller Interface (UFSHCI)standard by JEDEC Solid State Technology Association, 09/01/2013

INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICESstandard by JEDEC Solid State Technology Association, 10/01/2007

STANDARD FOR FAILURE ANALYSIS REPORT FORMATstandard by JEDEC Solid State Technology Association, 12/01/1995

EXTENSION OF THERMAL TEST BOARD STANDARDS FOR PACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMSstandard by JEDEC Solid State Technology Association, 02/01/1999

Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600Amendment by JEDEC Solid State Technology Association, 07/01/2010

LOW TEMPERATURE STORAGE LIFEstandard by JEDEC Solid State Technology Association, 11/01/2004